ATTACHMENT 1
SCHEDULE OF PATENTS

US 5,440,749 Hi Perf, Lo cost Micro Arch - issued Aug 1995
High-performance, low-cost micro-processor architecture
US 5,530,890 Hi Perf, Lo cost Micro Arch - Jun 95
US 5,659,703 Micro Sys with Hierarchical stack - Aug 97
US 5,784,584 Multiple Instructions within Groups - Jul 98
US 5,809,336 Hi Perf Variable Speed Sys Clock - Sep 98
US 5,604,915 Load Dependent Bus Timing - Feb 97
US 6,598,148 Hi Perf Variable Speed Sys Clock
DE 69033568.7 Hi Perf, Lo Cost Micro - Jun 00
DE 69033568T2 Preisguenstiger Hochleistungsmikro - Mar 01
DE 69033568C0 Preisguenstiger Hochleistungsmikro - Jul 00
EP 0786730 Hi Perf, Lo Cost Micro - Jun 00
EP 786730A1 Hi Perf, Lo Cost Micro - Jul 97
EP 497772A4 Hi Perf, Lo Cost Micro - Aug 93
EP 497772A1 Hi Perf, Lo Cost Micro - Aug 92
EP 0870226
FR 0786730 Hi Perf, Lo Cost Micro - Jul 00
WO 9715001 RISC Microprocessor Arch
WO 9102311A3 Hi Perf, Lo Cost Micro - Mar 91
WO 9102311A1 Hi Perf, Lo Cost Micro - Feb 91
JP 5502125T2 - Apr 93
JP 2966085B2 - Oct 99
AU 6067290A1 Hi Perf, Lo Cost Micro - Mar 91